This invention relates to semiconductor memory devices and in particular to a refreshing or regeneration means for such memories.
In a competitive, cost-sensitive business such as the computer industry, the need arises to maximize the performance and functionality of a computer system while minimizing the hardware costs.
One problem common to most computer designs is that of providing a highly accurate system clock (time-of-day) mechanism which requires little processor degredation (software or firmware overhead) to maintain. For this reason, all or part of the system clock function is frequently implemented via dedicated hardware. Another common problem in computer systems which use dynamic RAM memories to implement all or part of the system memory storage is that of providing the timing generation to control the refresh operation of the RAM memory components. The reason for requiring memory refresh is that dynamic memory cells store information as a function of electrical charge on a capacitor. A capacitor is a dynamic device in that the charge, representing the information stored, quickly dissipates. In prior art systems, the memory refresh is accomplished by having; a counter which provides the refresh address, and a system interrupt mechanism which allows the refresh to occur, all operating in conjunction with a timer to indicate when the refresh should occur. As previously stated, the cost of this circuitry in a competitive climate urges a solution which would eliminate this additional hardware cost.
Patents representing the state of memory refreshing known to the inventor at the time of filing this application are as follows:
U.S. Pat. No. 3,684,897 entitled "Dynamic MOS Memory Array Timing System" by S. R. Anderson; U.S. Pat. No. 4,079,462 entitled "Refreshing Apparatus for MOS Dynamic RAMs" by J. T. Koo; U.S. Pat. No. 4,207,618 entitled "On-Chip Refresh for Dynamic Memory" by L. S. White, Jr. et al.; and U.S. Pat. No. 4,249,247 entitled "Refesh System for Dynamic RAM Memory" by N. M. Patel.
In light of the present solutions to the refresh problem, the present invention is directed to the utilization of the real time system clock circuitry for a dual purpose, that is, for refresh address building in the RAS only (Row Address) type of refresh operation and for the basic operation of providing a time-of-day counter.